Hi, I am Zevorn. I work on foundational systems software, with a long-running focus on virtualization, architecture simulation, dynamic binary translation, and compiler/runtime infrastructure.
This blog is my technical notebook. Most posts are written from engineering work and experiments rather than from abstract summaries: debugging QEMU boards, modeling RISC-V behavior, analyzing LLVM and JIT internals, improving simulation performance, and turning research notes into reproducible workflows.
What I focus on
- Virtualization and emulation: QEMU machine models, TCG, KVM, tracing, debug tooling, and guest boot flows.
- RISC-V systems: vector extension behavior, debug specifications, server-platform reference models, openEuler RISC-V, and hardware-isolation proposals.
- Compiler and runtime infrastructure: LLVM, alias analysis, JIT code generation, AsmJit, dynamic binary translation, and floating-point emulation.
- AI-assisted engineering workflows: using agents to turn ideas into plans, patches, review loops, and delivered systems software.
Representative work notes
- QEMU Open-Source Community Contribution Log
- Optimizing QEMU RISC-V Vector Strided LD/ST for a 25× Speedup in Simulation
- QEMU RISC-V Server Platform (RVSP) Implementation Analysis
- Adding Floating-Point Precisions for Neural Network Computation to QEMU SoftFloat
- From Zero to Delivery: Best Practices for Agent-Collaborative Triton RISC-V CPU Backend Development
Links
- GitHub: github.com/zevorn
- Blog source and discussions: github.com/zevorn/blog
Contact
The best way to reach me for technical discussion is through GitHub Discussions, issues, or public project threads related to the topic.