Posts

From Zero to Delivery: Best Practices for Agent-Collaborative Triton RISC-V CPU Backend Development

I have used agents to recreate many tasks and ideas that fit within my stack, and the efficiency gains are obvious. But the way to stay competitive is not to fork work; it is to do

QEMU RISC-V Server Platform (RVSP) Implementation Analysis

Original Text Information Source: RISC V Developer Community Author / ID: zevorn Original post: https://ruyisdk.cn/t/topic/1913 Original publication date: 2025 11 10 Abstract The a

Running openEuler RISC-V 25.09 on QEMU's RISC-V Server Platform Reference (rvsp-ref)

Source information Source: RISC V Developer Community Author / ID: zevorn Original: https://ruyisdk.cn/t/topic/1836 Original publication date: 2025 11 01 Summary This article expla

WorldGuard: A Hardware-Level Isolation Specification for the RISC-V Architecture (Proposal Stage)

Source information Source: RISC V Developer Community Author / ID: zevorn Original: https://ruyisdk.cn/t/topic/1275 Original publication date: 2025 08 30 Summary This article expla

Exploring a New RISC-V Proposal: BF16 and Minimal OFP8 Vector Compute (Zvfbfa and Zvfofp8min)

Source information Source: RISC V Developer Community Author / ID: zevorn Original: https://ruyisdk.cn/t/topic/964 Original publication date: 2025 08 07 Summary This article discus

Exploring the Implementation of The RISC-V Debug Specification

Original Info Source: RISC V Developer Community Author / ID: zevorn Original: https://ruyisdk.cn/t/topic/919 Publication date: 2025 08 02 Abstract Against the backdrop of RISC V D

Deprecating QEMU xilinx_zynq Board Support for ignore_memory_transaction_failures

Original Info Source: TinyLab Technology Author: Chao Liu Original: https://tinylab.org/qemu drop ignore memory transaction failures/ Publication date: 2024 10 29 Abstract The arti

Optimizing QEMU RISC-V Vector Strided LD/ST for a 25× Speedup in Simulation

These past two days I was browsing the mailing list and found a QEMU TCG RVV performance optimization patch ( Re: PATCH 1/1 v2 RISC V/RVV Generate strided vector loads/stores with

Simulating MI300X with gem5 and Saving 100k?

A while ago, someone in the community published a Zhihu post on simulating MI300X with gem5 1 . Since I was recently verifying AMDGPU floating point precision, I wanted to compare

Adding Floating-Point Precisions for Neural Network Computation to QEMU SoftFloat

QEMU’s softfloat source code lives under the fpu/ and include/fpu/ paths. The code originally came from version 2a of the Berkeley SoftFloat IEC/IEEE floating point package (SoftFl

A Preliminary Look at Floating-Point Precision for AI FPU Virtual Prototyping Platforms for LLMs

This article first appeared on the WeChat public account GTOC. Quantization is widely used in industry to improve the training and inference efficiency of large models and reduce c

Virtualization from the Perspective of Interfaces

This article was first published on the GTOC WeChat account. It summarizes the virtual machine introduction chapter from the book Virtual Machine Systems and Processes: A General P