Ai-Infra

Exploring a New RISC-V Proposal: BF16 and Minimal OFP8 Vector Compute (Zvfbfa and Zvfofp8min)

Source information Source: RISC V Developer Community Author / ID: zevorn Original: https://ruyisdk.cn/t/topic/964 Original publication date: 2025 08 07 Summary This article discus

Adding Floating-Point Precisions for Neural Network Computation to QEMU SoftFloat

QEMU’s softfloat source code lives under the fpu/ and include/fpu/ paths. The code originally came from version 2a of the Berkeley SoftFloat IEC/IEEE floating point package (SoftFl

A Preliminary Look at Floating-Point Precision for AI FPU Virtual Prototyping Platforms for LLMs

This article first appeared on the WeChat public account GTOC. Quantization is widely used in industry to improve the training and inference efficiency of large models and reduce c