Floating-Point

Exploring a New RISC-V Proposal: BF16 and Minimal OFP8 Vector Compute (Zvfbfa and Zvfofp8min)

Source information Source: RISC V Developer Community Author / ID: zevorn Original: https://ruyisdk.cn/t/topic/964 Original publication date: 2025 08 07 Summary This article discus

Simulating MI300X with gem5 and Saving 100k?

A while ago, someone in the community published a Zhihu post on simulating MI300X with gem5 1 . Since I was recently verifying AMDGPU floating point precision, I wanted to compare

Adding Floating-Point Precisions for Neural Network Computation to QEMU SoftFloat

QEMU’s softfloat source code lives under the fpu/ and include/fpu/ paths. The code originally came from version 2a of the Berkeley SoftFloat IEC/IEEE floating point package (SoftFl

A Preliminary Look at Floating-Point Precision for AI FPU Virtual Prototyping Platforms for LLMs

This article first appeared on the WeChat public account GTOC. Quantization is widely used in industry to improve the training and inference efficiency of large models and reduce c

Simulating AArch64 FCMP Instructions on x86

The most efficient way to emulate an architecture is to get as close as possible to a 1:1 instruction mapping, where one source architecture instruction corresponds to one target a